1. Field of the Invention
The present invention relates generally to phase-locked loop circuits, and more specifically, to a design to reduce lock-time in a dual charge-pump phase-locked loop.
2. Background Information
Due to continual advancements in microprocessor design and fabrication techniques, the physical size of microprocessors has been decreased over time, while the clock frequencies of these microprocessors have continually been increased. In order to attain even higher clock frequencies in the future, much attention is currently being focused on increasing clock accuracy by reducing such things as clock skew and jitter, which can adversely affect the timing of a circuit or system.
Phase-locked loops or “PLLs” have been widely used in data communications, local area networks, microprocessors, and data storage applications to generate secondary clock signals based upon a given reference signal. FIG. 1 illustrates a phase-locked loop in accordance with the prior art. Conventional PLLs, such as PLL 100, generally include a phase-frequency detector (PFD) 102 for monitoring a phase difference between a reference signal 104 and a feedback signal 106 (in the form of a frequency divided output signal of a voltage-controlled oscillator (VCO) 108). The PFD 102 generates an UP control signal 110 and a DOWN control signal 112 to cause a charge pump 114 to respectively charge and discharge a loop filter 116. The loop control voltage 118 developed across the loop filter 116 determines the output frequency of the VCO 108. Furthermore, the UP and DOWN control signals 110, 112 driving the charge pump 114 set the proper loop filter control voltage 118 at the input of the VCO to maintain a minimal phase error between the input signals applied to the PFD 102.
During lock acquisition, the PFD attempts to correct for frequency differences and/or phase misalignments between the reference and feedback clocks 104, 106. The correction comes in the form of the UP/DOWN control signals 110, 112 whose pulse-widths are proportional to the frequency and/or phase error between the two input signals. The pulse width of the UP/DOWN control signals 110, 112 informs the charge-pump as to how much current to source or sink from loop filter capacitors. As such, a large error causing a large correction is common during the power-up process.
In a PLL containing dual charge-pumps, the primary charge pump adjusts a first control voltage that is associated with a large loop capacitor, and the secondary charge-pump adjusts a second control voltage that realizes a loop resistor. These two control voltages are routed to the VCO to generate an output clock with a frequency that is proportional to the respective control voltages. Since the second control voltage is held by only a small storage capacitor, its voltage ripples tend to be large during lock acquisition as a result of large frequency/phase errors. More specifically, a sufficiently large voltage change can force the VCO out of its linear, functional range resulting in an increased lock time and, in turn, decreased performance.